ARM_CLK_DIS_ON_LPM=ARM_CLK_DIS_ON_LPM_0, MASK_SCU_IDLE=MASK_SCU_IDLE_0, MASK_L2CC_IDLE=MASK_L2CC_IDLE_0, MASK_CORE0_WFI=MASK_CORE0_WFI_0, COSC_PWRDOWN=COSC_PWRDOWN_0, VSTBY=VSTBY_0, DIS_REF_OSC=DIS_REF_OSC_0, SBYOS=SBYOS_0, LPM=LPM_0, STBY_COUNT=STBY_COUNT_0
CCM Low Power Control Register
| LPM | Setting the low power mode that system will enter on next assertion of dsm_request signal. 0 (LPM_0): Remain in run mode 1 (LPM_1): Transfer to wait mode 2 (LPM_2): Transfer to stop mode |
| ARM_CLK_DIS_ON_LPM | Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait mode 0 (ARM_CLK_DIS_ON_LPM_0): ARM clock enabled on wait mode. 1 (ARM_CLK_DIS_ON_LPM_1): ARM clock disabled on wait mode. . |
| SBYOS | Standby clock oscillator bit 0 (SBYOS_0): On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - ‘0’ and cosc_pwrdown will remain de asserted - ‘0’) 1 (SBYOS_1): On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - ‘1’ and cosc_pwrdown will be asserted - ‘1’). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process. |
| DIS_REF_OSC | dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i 0 (DIS_REF_OSC_0): external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = ‘0’. 1 (DIS_REF_OSC_1): external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = ‘1’ |
| VSTBY | Voltage standby request bit 0 (VSTBY_0): Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - ‘0’) 1 (VSTBY_1): Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - ‘1’). |
| STBY_COUNT | Standby counter definition 0 (STBY_COUNT_0): CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles 1 (STBY_COUNT_1): CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles 2 (STBY_COUNT_2): CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles 3 (STBY_COUNT_3): CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles |
| COSC_PWRDOWN | In run mode, software can manually control powering down of on chip oscillator, i 0 (COSC_PWRDOWN_0): On chip oscillator will not be powered down, i.e. cosc_pwrdown = ‘0’. 1 (COSC_PWRDOWN_1): On chip oscillator will be powered down, i.e. cosc_pwrdown = ‘1’. |
| BYPASS_LPM_HS1 | Bypass low power mode handshake. This bit should always be set to 1’b1 by software. |
| BYPASS_LPM_HS0 | Bypass low power mode handshake. This bit should always be set to 1’b1 by software. |
| MASK_CORE0_WFI | Mask WFI of core0 for entering low power mode Assertion of all bits[27:22] will generate low power mode request 0 (MASK_CORE0_WFI_0): WFI of core0 is not masked 1 (MASK_CORE0_WFI_1): WFI of core0 is masked |
| MASK_SCU_IDLE | Mask SCU IDLE for entering low power mode Assertion of all bits[27:22] will generate low power mode request 0 (MASK_SCU_IDLE_0): SCU IDLE is not masked 1 (MASK_SCU_IDLE_1): SCU IDLE is masked |
| MASK_L2CC_IDLE | Mask L2CC IDLE for entering low power mode 0 (MASK_L2CC_IDLE_0): L2CC IDLE is not masked 1 (MASK_L2CC_IDLE_1): L2CC IDLE is masked |